Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor memory device that improves column repair efficiency.
A semiconductor memory device such as a dynamic random access memory (DRAM) includes a number of memory cells. If any one of the memory cells has a defect, the semiconductor memory device malfunctions and is treated as a defective product. Furthermore, the recent trend toward the high integration and high speed of semiconductor memory devices increases the probability of the occurrence of such defective cells, thus reducing the wafer yield that is represented as the ratio of the number of non-defective chips to the number of all chips fabricated on a wafer and determines the fabrication costs. Accordingly, a method for correcting defective cells to increase the wafer yield of highly integrated memory devices is desirable.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device for performing a conventional defective cell column repair method.
Referring to FIG. 1, a conventional semiconductor memory device includes a plurality of column memory cell blocks O0, O1, O2, O3, O4, O5, O6, and O7 disposed in a column direction. Each of the column memory cell blocks O0, O1, O2, O3, O4, O5, O6, and O7 includes a plurality of normal column cell lines 0NSYI, 1NSYI, 2NSYI, 3NSYI, 4NSYI, 5NSYI, 6NSYI, and 7NSYI, and a plurality of redundancy column cell lines 0RSYI, 1RSYI, 2RSYI, 3RSYI, 4RSYI, 5RSYI, 6RSYI, and 7RSYI.
Thus, if a fail occurs in the normal column cell lines 0NSYI, 1NSYI, 2NSYI, 3NSYI, 4NSYI, 5NSYI, 6NSYI, and 7NSYI included in each of the column memory cell blocks O0, O1, O2, O3, O4, O5, O6, and O7, a redundancy operation is performed to repair the fail using the redundancy column cell lines 0RSYI, 1RSYI, 2RSYI, 3RSYI, 4RSYI, 5RSYI, 6RSYI, and 7RSYI included in the same column memory cell blocks O0, O1, O2, O3, O4, O5, O6, and O7.
However, if the number of normal column cell lines with a fail among the normal column cell lines 0NSYI, 1NSYI, 2NSYI, 3NSYI, 4NSYI, 5NSYI, 6NSYI, and 7NSYI included in each of the column memory cell blocks O0, O1, O2, O3, O4, O5, O6, and O7 is greater than the number of redundancy column cell lines 0RSYI, 1RSYI, 2RSYI, 3RSYI, 4RSYI, 5RSYI, 6RSYI, and 7RSYI included in the same column memory cell blocks O0, O1, O2, O3, O4, O5, O6, and O7, the conventional redundancy operation method cannot perform a normal repair operation.
In particular, even if free redundancy column cell lines are present in some of the column memory cell blocks O0, O1, O2, O3, O4, O5, O6, and O7, other cell blocks cannot share the free redundancy column cell lines. Therefore, the conventional redundancy operation method cannot perform a normal repair operation.
The disadvantages of the conventional redundancy operation may become a bigger concern as the technology of semiconductor memory devices advances (SDR-→DDR-→DDR2-→DDR3).
That is, because the number of pre-fetch bits increases as semiconductor memory device technology develops, the number of column memory cell blocks included in one bank increases. Accordingly, the number of redundancy column cell lines included in each column memory cell block decreases. Therefore, the number of normal column cell lines coverable in the event of the occurrence of a fail decreases. This undesirably reduces the possibility of performing a normal redundancy operation.
For reference, because an operation of repairing a row line in a general semiconductor memory device does not directly apply input/output data information, redundancy row cell lines can be directly shared among a plurality of row memory cell blocks.
However, because an operation of repairing a column line must directly apply input/output data information, redundancy column cell lines cannot be directly shared among a plurality of column memory cell blocks.